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| (R) EL5123, EL5223, EL5323, EL5423 Data Sheet August 31, 2010 FN7176.3 12MHz 4-, 8-, 10- and 12-Channel Rail-to-Rail Input-Output Buffers The EL5123, EL5223, EL5323, and EL5423 are low power, high voltage rail-to-rail input/output buffers designed primarily for use in reference voltage buffering applications for TFT-LCDs. They are available in quad (EL5123), octal (EL5223), 10-Channel (EL5323), and 12-Channel (EL5423) topologies. All buffers feature a -3dB bandwidth of 12MHz and operate from just 600A per buffer. This family also features fast slewing and settling times, as well as a continuous output drive capability of 30mA (sink and source). The quad channel EL5123 is available in the 10 Ld MSOP package. The 8-Channel EL5223 is available in both the 20 Ld TSSOP and 24 Ld QFN packages, the 10-Channel EL5323 in the 24 Ld TSSOP and 24 Ld QFN packages, and the 12-Channel EL5423 in the 28 Ld TSSOP and 32 Ld QFN packages. All buffers are specified for operation over the full -40C to +85C temperature range. Features * 12MHz -3dB bandwidth * Supply voltage = 4.5V to 16.5V * Low supply current (per buffer) = 600A * High slew rate = 15V/s * Rail-to-rail input/output swing * Ultra-small packages * Pb-Free Available (RoHS Compliant) Applications * TFT-LCD drive circuits * Electronics notebooks * Electronic games * Touch-screen displays * Personal communication devices * Personal digital assistants (PDA) * Portable instrumentation * Sampling ADC amplifiers * Wireless LANs * Office automation * Active filters * ADC/DAC buffers 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002-2004, 2007, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5123, EL5223, EL5323, EL5423 Pinouts EL5223, EL5323 (24 LD QFN) TOP VIEW 21 VOUT1* 20 VOUT2 23 VIN1* 24 VIN2 22 NC VIN1 1 VIN2 2 19 VOUT3 18 VOUT4 17 VOUT5 THERMAL PAD** 16 VS15 VOUT6 14 VOUT7 13 VOUT8 NC 10 VOUT10* 11 CVIN10* 9 VOUT9 12 VIN9 8 VS+ 3 VIN3 4 VIN4 5 EL5123 (10 LD MSOP) TOP VIEW 10 VOUT1 9 VOUT2 8 VS7 VOUT3 6 VOUT4 VIN1 1 VIN2 2 VIN3 3 VIN4 4 VS+ 5 VS+ 6 VIN5 7 VIN6 8 VIN7 9 EL5223 (20 LD TSSOP) TOP VIEW 20 VOUT1 19 VOUT2 18 VOUT3 17 VOUT4 16 VS15 VS14 VOUT5 13 VOUT6 12 VOUT7 11 VOUT8 VIN3 1 VIN4 2 VIN5 3 VS+ 4 VIN6 5 VIN7 6 VIN8 7 VIN8 10 * NOT AVAILABLE IN EL5223 * *THERMAL PAD CONNECTS TO VS- EL5423 (32 LD QFN) TOP VIEW 27 VOUT1 26 VOUT2 32 VIN2 31 VIN1 30 NC 29 NC 28 NC VIN1 1 VIN2 2 25 VOUT3 24 VOUT4 23 VOUT5 22 VOUT6 THERMAL PAD** 21 VS20 VOUT7 19 VOUT8 18 VOUT9 17 VOUT10 VIN11 10 VIN12 11 NC 12 NC 13 NC 14 VOUT12 15 VOUT11 16 VIN3 3 VIN4 4 VIN5 5 VIN6 6 VS+ 7 VS+ 8 VIN7 9 EL5423 (28 LD TSSOP) TOP VIEW 28 VOUT1 27 VOUT2 26 VOUT3 25 VOUT4 24 VOUT5 23 VOUT6 22 VS21 VS20 VOUT7 19 VOUT8 18 VOUT9 17 VOUT10 16 VOUT11 15 VOUT12 VIN1 1 VIN2 2 VIN3 3 VIN4 4 VIN5 5 VS+ 6 VS+ 7 VIN6 8 VIN7 9 EL5323 (24 LD TSSOP) TOP VIEW 24 VOUT1 23 VOUT2 22 VOUT3 21 VOUT4 20 VOUT5 19 VS18 VS17 VOUT6 16 VOUT7 15 VOUT8 14 VOUT9 13 VOUT10 VIN3 1 VIN4 2 VIN5 3 VIN6 4 VS+ 5 VIN7 6 VIN8 7 VIN9 8 VIN10 9 VIN8 10 VIN9 11 VIN10 12 VIN11 13 VIN12 14 VIN8 10 VIN9 11 VIN10 12 * *THERMAL PAD CONNECTS TO VS- 2 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Ordering Information PART NUMBER EL5123CY EL5123CY-T7* EL5123CY-T13* EL5123CYZ (Note) EL5123CYZ-T7* (Note) EL5123CYZ-T13* (Note) EL5223CL EL5223CL-T7* EL5223CL-T13* EL5223CLZ (Note) EL5223CLZ-T7* (Note) EL5223CLZ-T13* (Note) EL5223CR EL5223CR-T7* EL5223CR-T13* EL5223CRZ (Note) EL5223CRZ-T7* (Note) EL5223CRZ-T13* (Note) EL5323CL EL5323CL-T7* EL5323CL-T13* EL5323CLZ (Note) EL5323CLZ-T7* (Note) EL5323CLZ-T13* (Note) EL5323CR EL5323CR-T13* EL5323CRZ (Note) EL5323CRZ-T7* (Note) EL5323CRZ-T13* (Note) EL5423CL EL5423CL-T7* EL5423CL-T13* EL5423CLZ (Note) EL5423CLZ-T7* (Note) EL5423CLZ-T13* (Note) P P P BAAAT BAAAT BAAAT 5223CL 5223CL 5223CL 5223CLZ 5223CLZ 5223CLZ 5223CR 5223CR 5223CR 5223CRZ 5223CRZ 5223CRZ 5323CL 5323CL 5323CL 5323CLZ 5323CLZ 5323CLZ 5323CR 5323CR 5323CRZ 5323CRZ 5323CRZ 5423CL 5323CL 5423CL 5423CLZ 5423CLZ 5423CLZ PART MARKING PACKAGE 10 Ld MSOP (3.0mm) 10 Ld MSOP (3.0mm) 10 Ld MSOP (3.0mm) 10 Ld MSOP (3.0mm) (Pb-free) 10 Ld MSOP (3.0mm) (Pb-free) 10 Ld MSOP (3.0mm) (Pb-free) 24 Ld QFN (4mmx5mm) 24 Ld QFN (4mmx5mm) 24 Ld QFN (4mmx5mm) 24 Ld QFN (4mmx5mm) (Pb-free) 24 Ld QFN (4mmx5mm) (Pb-free) 24 Ld QFN (4mmx5mm) (Pb-free) 20 Ld TSSOP (4.4mm) 20 Ld TSSOP (4.4mm) 20 Ld TSSOP (4.4mm) 20 Ld TSSOP (4.4mm) (Pb-free) 20-Ld TSSOP (4.4mm) (Pb-free) 20 Ld TSSOP (4.4mm) (Pb-free) 24 Ld QFN (4mmx5mm) 24 Ld QFN (4mmx5mm) 24 Ld QFN (4mmx5mm) 24 Ld QFN (4mmx5mm) (Pb-free) 24 Ld QFN (4mmx5mm) (Pb-free) 24 Ld QFN (4mmx5mm) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld TSSOP (4.4mm) (Pb-free) 32 Ld QFN (5mmx6mm) 32 Ld QFN (5mmx6mm) 32 Ld QFN (5mmx6mm) 32 Ld QFN (5mmx6mm) (Pb-free) 32 Ld QFN (5mmx6mm) (Pb-free) 32 Ld QFN (5mmx6mm) (Pb-free) PKG. DWG. # MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0044 MDP0044 MDP0044 M20.173 M20.173 M20.173 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0044 MDP0044 MDP0044 MDP0044 MDP0044 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 3 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Ordering Information (Continued) PART NUMBER EL5423CR EL5423CR-T7* EL5423CR-T13* EL5423CRZ (Note) EL5423CRZ-T7* (Note) EL5423CRZ-T13* (Note) PART MARKING 5423CR 5423CR 5423CR 5423CRZ 5423CRZ 5423CRZ PACKAGE 28 Ld TSSOP (4.4mm) 28 Ld TSSOP (4.4mm) 28 Ld TSSOP (4.4mm) 28 Ld TSSOP (4.4mm) (Pb-free) 28 Ld TSSOP (4.4mm) (Pb-free) 28 Ld TSSOP (4.4mm) (Pb-free) PKG. DWG. # MDP0044 MDP0044 MDP0044 MDP0044 MDP0044 MDP0044 *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Absolute Maximum Ratings (TA = +25C) Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA ESD Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA NOTES: 1. Measured over operating temperature range. 2. Instantaneous peak current. 3. Slew rate is measured on rising and falling edges Electrical Specifications PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV VS+ = +5V, VS- = -5V, RL = 10k and CL = 10pF to 0V, TA = +25C, Unless Otherwise Specified. CONDITION MIN TYP MAX UNIT DESCRIPTION Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain VCM = 0V (Note 1) VCM = 0V 0.5 5 2 1 1.35 12 mV V/C 50 nA G pF -4.5V VOUT 4.5V 0.99 1.01 V/V OUTPUT CHARACTERISTICS VOL VOH IOUT (max) Output Swing Low Output Swing High Output Current (Note 2) IL = -5mA IL = +5mA RL = 10 4.85 -4.95 4.95 120 -4.85 V V mA POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current VS is moved from 2.25V to 7.75V No load (EL5123) No load (EL5223) No load (EL5323) No load (EL5423) DYNAMIC PERFORMANCE SR tS BW CS Slew Rate (Note 3) Settling to +0.1% (AV = +1) -3dB Bandwidth Channel Separation -4.0V VOUT 4.0V, 20% to 80% (AV = +1), VO = 2V step RL = 10k, CL = 10pF f = 5MHz 7 15 250 12 75 V/s ns MHz dB 55 80 2.4 5.5 6 7.45 3.4 6.8 8.5 10.1 dB mA mA mA mA 5 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Electrical Specifications PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain 0.5V VOUT 4.5V 0.99 VCM = 2.5V (Note 1) VCM = 2.5V 0.5 5 2 1 1.35 1.01 50 12 mV V/C nA G pF V/V VS+ =+5V, VS- = 0V, RL = 10k and CL = 10pF to 2.5V, TA = +25C, Unless Otherwise Specified. CONDITION MIN TYP MAX UNIT DESCRIPTION OUTPUT CHARACTERISTICS VOL VOH IOUT (max) Output Swing Low Output Swing High Output Current (Note 2) IL = -2.5mA IL = +2.5mA RL = 10 4.85 80 4.92 120 150 mV V mA POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current VS is moved from 4.5V to 15.5V No load (EL5123) No load (EL5223) No load (EL5323) No load (EL5423) DYNAMIC PERFORMANCE SR tS BW CS Slew Rate (Note 3) Settling to +0.1% (AV = +1) -3dB Bandwidth Channel Separation 1V VOUT 4V, 20% to 80% (AV = +1), VO = 2V step RL = 10k, CL = 10pF f = 5MHz 12 250 12 75 V/s ns MHz dB 55 80 2.4 5.2 5.8 7.2 3.2 6.5 8 9.7 dB mA mA mA mA Electrical Specifications PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV VS+ = +15V, VS- = 0V, RL = 10k and CL = 10pF to 7.5V, TA = +25C, Unless Otherwise Specified. CONDITION MIN TYP MAX UNIT DESCRIPTION Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain VCM = 7.5V (Note 1) VCM = 7.5V 0.5 5 2 1 1.35 14 mV V/C 50 nA G pF 0.5V VOUT 14.5V 0.99 1.01 V/V OUTPUT CHARACTERISTICS VOL VOH IOUT (max) Output Swing Low Output Swing High Output Current (Note 2) IL = -7.5mA IL = +7.5mA RL = 10 14.85 120 80 14.95 200 150 mV V mA 6 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Electrical Specifications PARAMETER VS+ = +15V, VS- = 0V, RL = 10k and CL = 10pF to 7.5V, TA = +25C, Unless Otherwise Specified. CONDITION MIN TYP MAX UNIT DESCRIPTION POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current VS is moved from 4.5V to 15.5V No load (EL5123) No load (EL5223) No load (EL5323) No load (EL5423) DYNAMIC PERFORMANCE SR tS BW CS Slew Rate (Note 3) Settling to +0.1% (AV = +1) -3dB Bandwidth Channel Separation 1V VOUT 14V, 20% to 80% (AV = +1), VO = 2V step RL = 10k, CL = 10pF f = 5MHz 18 250 12 75 V/s ns MHz dB 55 80 2.4 5.7 6.2 7.8 3.7 7.1 8.7 10.4 dB mA mA mA mA 7 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Typical Performance Curves 12 10 8 VOP-P (V) 6 4 2 THD + NOISE (%) 0.018 0.016 0.014 0.012 0.01 0.008 0.006 1k VS = 5V RL = 10k VIN = 2VP-P 0 10k VS = 5V RL = 10k 100k 1M 10M 10k FREQUENCY (Hz) 100k FREQUENCY (Hz) FIGURE 1. OUTPUT SWING vs FREQUENCY FIGURE 2. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 80 70 OVERSHOOT (%) 60 50 40 30 20 10 0 10 VS = 5V RL = 10k VIN = 100mV STEP SIZE (V) 10 6 VS = 5V RL = 10k CL = 12pF 2 -2 -6 100 CAPACITANCE (pF) 1k -10 200 250 300 350 400 450 500 550 600 650 SETTLING TIME (ns) FIGURE 3. OVERSHOOT vs LOAD CAPACITANCE FIGURE 4. SETTLING TIME vs STEP SIZE 20 NORMALIZED MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) VS = 5V RL = 10k 20 1000pF 100pF 10 VS = 5V CL = 10pF 1k 10 0 47pF -10 12pF 0 -10 562 -20 -30 100k 150 10k -20 -30 100k 1M 10M 100M 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS CL FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS RL 8 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Typical Performance Curves (Continued) 100 PSRR+ 80 PSRR (dB) PSRROUTPUT IMPEDANCE () 480 600 VS = 5V TA = +25C 60 360 40 240 20 VS = 5V 10k 100k FREQUENCY (Hz) 1M 10M 120 0 1k 0 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 7. PSRR vs FREQUENCY FIGURE 8. OUTPUT IMPEDANCE vs FREQUENCY 25 VOLTAGE NOISE (nV/Hz) 100 20 % OF BUFFERS 15 10 10 5 -6 -4 -2 1 10k 100k 1M FREQUENCY (Hz) 10M 100M 0 0 2 4 INPUT OFFSET VOLTAGE (mV) 6 85 FN7176.3 August 31, 2010 FIGURE 9. INPUT NOISE SPECTRAL DENSITY vs FREQUENCY FIGURE 10. INPUT OFFSET VOLTAGE DISTRIBUTION 2.5 INPUT BIAS CURRENT (nA) VS = 5V OUTPUT HIGH VOLTAGE (V) 4.955 4.950 4.945 4.940 4.935 4.930 4.925 1.5 0.5 -0.5 -1.5 -2.5 VS = 5V IOUT = 5mA -35 -15 5 25 45 65 -35 -15 5 25 45 65 85 TEMPERATURE (C) TEMPERATURE (C) FIGURE 11. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 12. OUTPUT HIGH VOLTAGE vs TEMPERATURE 9 EL5123, EL5223, EL5323, EL5423 Typical Performance Curves (Continued) 15.1 VS = 5V OUTPUT LOW VOLTAGE (V) -4.934 VS = 5V IOUT = -5mA 14.9 SLEW RATE (V/s) -4.938 14.7 -4.942 14.5 -4.946 14.3 -4.950 14.1 -35 -15 5 25 45 65 85 -4.954 -35 -15 5 25 45 65 85 TEMPERATURE (C) TEMPERATURE (C) FIGURE 13. SLEW RATE vs TEMPERATURE FIGURE 14. OUTPUT LOW VOLTAGE vs TEMPERATURE 1.0014 VS = 5V SUPPLY CURRENT (mA) 0.66 VS = 5V VOLTAGE GAIN (V/V) 1.0010 0.65 1.0006 0.64 1.0000 0.63 0.9998 -35 -15 5 25 45 65 85 TEMPERATURE (C) 0.62 -35 -15 5 25 45 65 85 TEMPERATURE (C) FIGURE 15. VOLTAGE GAIN vs TEMPERATURE FIGURE 16. SUPPLY CURRENT PER CHANNEL vs TEMPERATURE 0.71 TA = +25C VS = 5V RL = 10k CL = 12pF SUPPLY CURRENT (mA) 0.69 0.67 50mV/DIV 0.65 0.63 4 6 8 10 12 14 16 18 200ns/DIV SUPPLY VOLTAGE (V) FIGURE 17. SUPPLY CURRENT PER CHANNEL vs SUPPLY VOLTAGE FIGURE 18. SMALL SIGNAL TRANSIENT RESPONSE 10 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Typical Performance Curves (Continued) JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD, QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 2.857W 3.0 POWER DISSIPATION (W) 2.5 2.703W 2.0 1.5 1.0 0.5 0 QFN24 JA = +37C/W QFN32 JA = +35C/W 1V/DIV 1s/DIV 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) FIGURE 19. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 0.8 0.7 POWER DISSIPATION (W) 0.6 0.5 0.4 0.3 0.2 0.1 0 JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 758mW POWER DISSIPATION (W) 714mW QFN32 JA = +132C/W 1.4 1.2 1.0 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.333W 1.176W 1.111W TSSOP24 JA = +85C/W TSSOP28 JA = +75C/W QFN24 JA = +140C/W 0.8 870mW 0.6 0.4 0.2 0 0 25 TSSOP20 JA = +95C/W MSOP10 JA = +115C/W 50 0 25 50 75 85 100 125 150 75 85 100 125 150 AMBIENT TEMPERATURE (C) AMBIENT TEMPERATURE (C) FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 0.9 0.8 POWER DISSIPATION (W) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 833mW 781mW 714mW TSSOP24 JA = +128C/W TSSOP28 JA = +120C/W 486mW MSOP10 JA = +206C/W TSSOP20 JA = +140C/W 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 11 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Applications Information Product Description The EL5123, EL5223, EL5323, and EL5423 unity gain buffers are fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability and has low power consumption (600A per buffer). These features make the EL5123, EL5223, EL5323, and EL5423 ideal for a wide range of general-purpose applications. When driving a load of 10k and 12pF, the EL5123, EL5223, EL5323, and EL5423 have a -3dB bandwidth of 12MHz and exhibits 15V/s slew rate. Output Phase Reversal The EL5123, EL5223, EL5323, and EL5423 are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 25 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's over-voltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. 1V 10s Operating Voltage, Input, and Output The EL5123, EL5223, EL5323, and EL5423 are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5123, EL5223, EL5323, and EL5423 specifications are stable over both the full supply range and operating temperatures of -40C to +85C. Parameter variations with operating voltage and/or temperature are shown in the "Typical Performance Curves" on page 8. The output swings of the EL5123, EL5223, EL5323, and EL5423 typically extend to within 50mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 24 shows the input and output waveforms for the device. Operation is from 5V supply with a 10k load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P. 5V 10s VS = 5V TA = +25C VIN = 10VP-P 1V VS=2.5V TA=25C VIN=6VP-P FIGURE 25. OPERATION WITH BEYOND-THE-RAILS INPUT Power Dissipation With the high-output drive capability of the EL5123, EL5223, EL5323, and EL5423 buffer, it is possible to exceed the +125C "absolute-maximum junction temperature" under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 1: T JMAX - T AMAX P DMAX = -------------------------------------------d JA (EQ. 1) OUTPUT INPUT where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature 5V FIGURE 24. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT JA = Thermal resistance of the package PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = i [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ] (EQ. 2) Short Circuit Current Limit The EL5123, EL5223, EL5323, and EL5423 will limit the short circuit current to 120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds 30mA. This limit is set by the design of the internal metal interconnects. 12 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 when sourcing, and P DMAX = i [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ] (EQ. 3) Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1F ceramic capacitor should be placed from VS+ pin to ground. A 4.7F tantalum capacitor should then be connected from VS+ pin to ground. One 4.7F capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. when sinking. where: i = 1 to Total number of buffers VS = Total supply voltage ISMAX = Maximum quiescent current per channel VOUTi = Maximum output voltage of the application ILOADi = Load current If we set the Equations 2 and 3 equal to each other, we can solve for RLOADi to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. Unused Buffers It is recommended that any unused buffer have the input tied to the ground plane. Driving Capacitive Loads The EL5123, EL5223, EL5323, and EL5423 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The buffers drive 10pF loads in parallel with 10k with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 50) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a "snubber" circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150 and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain. 13 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Mini SO Package Family (MSOP) 0.25 M C A B D N A (N/2)+1 MDP0043 MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. E E1 PIN #1 I.D. A2 b c B 1 D (N/2) E E1 e C SEATING PLANE 0.10 C N LEADS b H e L L1 0.08 M C A B N L1 A c SEE DETAIL "X" 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. A2 GAUGE PLANE A1 L DETAIL X 0.25 3 3 14 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 QFN (Quad Flat No-Lead) Package Family A D N (N-1) (N-2) B MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) MILLIMETERS SYMBOL QFN44 QFN3 A A1 b 0.90 0.02 0.25 0.20 7.00 5.10 7.00 5.10 0.50 0.55 44 11 11 0.90 0.02 0.25 0.20 5.00 3.80 7.00 5.80 0.50 0.40 38 7 12 QFN32 0.90 0.02 0.23 0.20 8.00 8.00 0.80 0.53 32 8 8 0.90 0.02 0.22 0.20 5.00 6.00 0.50 0.50 32 7 9 TOLERANCE 0.10 +0.03/-0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference NOTES 8 8 4 6 5 1 2 3 PIN #1 I.D. MARK E c D D2 E 5.80 3.60/2.48 5.80 4.60/3.40 (N/2) 2X 0.075 C E2 2X 0.075 C e L N ND NE TOP VIEW N LEADS 0.10 M C A B (N-2) (N-1) N b L PIN #1 I.D. 3 1 2 3 MILLIMETERS SYMBOL QFN28 QFN2 A A1 b 0.90 0.02 0.25 0.20 4.00 2.65 5.00 3.65 0.50 0.40 28 6 8 0.90 0.02 0.25 0.20 4.00 2.80 5.00 3.80 0.50 0.40 24 5 7 QFN20 0.90 0.02 0.30 0.20 5.00 3.70 5.00 3.70 0.65 0.40 20 5 5 0.90 0.02 0.25 0.20 4.00 2.70 4.00 2.70 0.50 0.40 20 5 5 QFN16 0.90 0.02 0.33 0.20 4.00 2.40 4.00 2.40 0.65 0.60 16 4 4 TOLERANCE NOTES 0.10 +0.03/ -0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference 4 6 5 (E2) NE 5 (N/2) c D D2 E E2 e L N ND NE (D2) BOTTOM VIEW 7 e C SEATING PLANE 0.08 C N LEADS & EXPOSED PAD 0.10 C Rev 11 2/07 SEE DETAIL "X" SIDE VIEW NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. (c) C A 2 5. NE is the number of terminals on the "E" side of the package (or Y-direction). (L) 6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. A1 DETAIL X N LEADS 15 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M20.173 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c MIN 0.002 0.031 0.0075 0.0035 0.252 0.169 0.246 0.0177 20 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.260 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 6.40 4.30 6.25 0.45 20 8o MAX 1.20 0.15 1.05 0.30 0.20 6.60 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 1 6/98 e b 0.10(0.004) M C AM BS A1 0.10(0.004) A2 c D E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 16 FN7176.3 August 31, 2010 EL5123, EL5223, EL5323, EL5423 Thin Shrink Small Outline Package Family (TSSOP) 0.25 M C A B D N (N/2)+1 A MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE A A1 0.20 C B A PIN #1 I.D. E E1 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00 Max 0.05 0.05 +0.05/-0.06 +0.05/-0.06 0.10 Basic 0.10 Basic 0.15 Reference Rev. F 2/07 A2 b c D E E1 1 B TOP VIEW (N/2) 2X N/2 LEAD TIPS C SEATING PLANE e 0.05 H e L L1 b 0.10 C N LEADS SIDE VIEW 0.10 M C A B NOTES: 1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions "D" and "E1" are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. SEE DETAIL "X" c END VIEW L1 A2 GAUGE PLANE 0.25 A1 DETAIL X L 0 - 8 A All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN7176.3 August 31, 2010 |
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